High density dynamic random access memorys (DRAMs) and static random access memorys (SRAMs) have long data lines for routing the memory cell information from the memory array to the output logic and output drivers at the periphery of the chip. These long data lines have large parasitic capacitances which limit the maximum operating frequency of the device. One method of improving the speed of the device is to reduce the length of the data lines by subdividing the memory array into smaller sections. However, this method is not always practical due to limitations in die size, packaging constraints, and other architectural layout limitations.
Many techniques have been employed for sensing the differential signal developed on the DRAM digit lines, amplifying the signal, and transmitting it to the output buffers. One method commonly used in DRAMs is to sense the signal with n and p-channel sense amplifiers, drive this differential potential to the end of the array, and amplify the differential potential with DC sense amplifiers located at the end of the array. The output of the DC sense amplifiers are used to drive the output logic located in the chip periphery.
With this approach the data lines develop a differential potential relatively slowly due to the low drive of the sense amp and the large RC time constant of the digit line, I/O line and data line combination. Specifically, the n and p-channel sense amplifiers are designed to have low drive capability in order to reduce power dissipation, since as many as 256 sense amps are turned on at once (the entire row). These sense amps drive the data lines through a column decode transistors 1 and an I/O line-to-data line multiplexer transistors 5, see FIG. 1. These transistors 5 have a drain-to-source resistance which increases the RC time constant of the circuit. Further, the capacitive load of the I/O lines 10 and data lines 11 combination is relatively large due to the number of column decode transistors 1 connected to the I/O lines 10, and due to the long lengths of data lines 11.
Another approach that is used in sensing the potential of the I/O lines is the addition of a helper flip-flop. With a helper flip-flop, the I/O lines are allowed to develop sufficient differential potential prior to clocking the flip-flop with an enable signal. While enabled, the helper flip-flop uses positive feedback to pull the true and complement output signals towards opposite supply potentials, thus amplifying the input signal. The large level differential output potential can be used to drive the input of a buffer circuit for driving the large capacitive load of the data lines. Sometimes, an additional helper flip-flop is used at the end of the data lines.
The advantage of a helper flip-flop is that the data lines are buffered from the I/O and digit lines, and a lower output impedance buffer circuit is used to drive the capacitive data lines. The disadvantage of this approach is that adequate signal must be developed prior to clocking the flip-flop to ensure that the output transitions to the correct state. Thus, the flip-flop must be clocked each time a new memory bit is accessed.
With either architecture, DC sense amp or helper flip-flop, the I/O and data lines are equilibrated and precharged to some operating point prior to turning on the column decoder gate and transferring the digit line differential potential. This is done to improve the speed, because the I/O and data lines now transition from midpoint to new state instead of from old state to new state. With a DC sense amp, the I/O and data lines are precharged to a potential compatible with the quiescent operating point of the amplifier, usually on the order of 0.6 V.sub.cc. With the helper flip-flop the I/O and data lines are usually precharged to V.sub.cc, and the output changes state when one of the data lines (true or complement) transitions to the opposite state, ground in this case.
With the helper flip-flop some speed is lost and some power is dissipated in each access cycle, since the data line transitions from V.sub.cc to ground and is precharged back to V.sub.cc prior to transitioning back to ground. Since the data lines have a large capacitive load, it takes significant time for the lines to transition between each power supply level. Also, power is dissipated in precharging and discharging the capacitances.
The output of the helper flip-flop usually drives a data latch which is used to store the data result while the data lines precharged. The latch 15 is shown in FIG. 2. The latch is constructed in a manner such that the latch holds the previous data when the data lines are both high, and the latch is set or reset when one of the data lines transitions low. The input of the latch can be designed to have a high trip point to improve and reduce the time required to transition to a new state.
FIG. 3 shows the schematic of a helper flip-flop buffer circuit. Transistors 20 and 25 comprise the cross-coupled differential transistor pair and transistor 30 is the current source for the helper flip-flop 35. The helper flip-flop 35 is clocked by a strobing signal, ENNSA, available at terminal 40. Transistors 45, 50, and 55 are used to precharge and equilibrate the helper flip-flop 35 to V.sub.cc. Transistors 60 and 65 are pass devices used to isolate the I/O lines 70 from the flip-flop 35 just prior to strobing the flip-flop 35. Transistors 75, 80, and 85 are used to precharge and equilibrate the data lines 90 and 95 to V.sub.cc. The buffer section 96 comprises differential pair transistors 100 and 105 and comprises the current source transistor 110. Capacitors 115 and 120 have been used to model the data line parasitic capacitance load.
FIG. 4 shows a typical timing sequence for the schematic of FIG. 3. The I/O lines 70 have been initially precharged to V.sub.cc (5v) by an I/O line precharge circuit not shown. During the precharge time the helper flip-flop internal nodes 111 and 112 and data lines 90 and 95 are precharged to V.sub.cc by a low CEQ* signal at terminal 113; the flip-flop and buffer section 96 is turned off since the signal at the ENNSA terminal 40 is low. At this time, the helper flip-flop 35 is also isolated from the I/O lines 70 by a high HFFISO* signal at terminal 114.
Differential potential is allowed to develop on the I/O lines at the start of an access cycle. At this time the equilibration is released (CEQ* goes high) and the helper flip-flop is connected to the I/O lines through the pass devices 60 and 65 (HFFISO* goes low). A small differential potential then develops on the helper flip-flop internal nodes 111 and 112. The potentials on internal nodes 111 and 112 are referred to as HFF and HFF* respectively. After sufficient potential has developed, the helper flip-flop 35 is isolated from the I/O lines (HFFISO* goes high) and ENNSA goes high which enables the buffer section 96. The internal flip-flop nodes 111 and 112 rapidly separate in potential due to the positive feedback of the helper flip-flop 35. These signals then drive the buffer section 96 which causes one of data lines 90 and 95 to be pulled to a low state, in this case complimentary data line (DL*) 95. After the data line has reached its ground potential, the helper circuit flip-flop 35 can be disabled (ENNSA goes low), and I/O lines 70 and data lines 90 and 95 can be precharged for the next access cycle. In the figure, data line (DL) 90 starts to momentarily go low by 1.5 volts; however, this is due to the equilibrate device. After sufficient precharge time, both data lines 90 and 95 will return to V.sub.cc.
The speed of an access cycle can be improved in a helper flip-flop design by only allowing the data lines to transition to a predetermined margin past the trip point of the data latch, as opposed to transitioning all the way to ground. Cycle time is improved because the data lines take less time to precharge from this level. A data line clamping circuit can be used for this purpose; however, power is dissipated in the clamping circuit.
FIG. 5 shows the same schematic as FIG. 3 with diode clamps 200 and 205 added to the data lines to limit their potential swing. The clamps can be sized appropriately to clamp the potential at the desired level. FIG. 6 shows the timing for this circuit which is identical to FIG. 2 except for the data line potentials. Note that the potential of complimentary data line 95 only reaches 2.5v due to the clamps, and therefore precharges back to V.sub.cc faster. If we assume that the trip point of the output latch is at 3v, then the output latch will switch later than in the previous circuit. This is due to the exponential transition of the data line, where the data line now exponentially approaches 2.5v instead of Ov. This is because the pull-down drive current of transistor 100 or 105 is opposed by the clamping pull-up current of transistor 200 or 205, respectively. In this case since the trip point is closer to the exponential final value, it takes longer for complimentary data line to reach the trip point potential. Further, more power is dissipated in this circuit since a DC current path exists from Vcc to ground via transistors 200, 100, and 110 or transistors 205, 105, and 110.
What would be most desireable is to have a signal that approaches ground at the same rate as in the circuit of FIG. 1, but stops abruptly, not exponentially, at some intermediate potential level. Further, it is desired to achieve this signal waveform without introducing more power dissipation as in the circuit of FIG. 5 comprising the diode clamps. The described invention accomplishes these goals, and thereby improves on the prior art.